1. Field of the Invention
This invention relates to a semiconductor device which can prevent a dopant contained in a non-single-crystal silicon film for determining its conductivity type from diffusing into a metal silicide film, and therefore has improved device characteristics. The invention also relates to a method for manufacturing such a semiconductor device.
2. Description of the Related Art
FIG. 17 is a cross sectional view showing the construction of a first conventional semiconductor device, which is an NMOS transistor. In the drawing, reference numeral 1 denotes a semiconductor substrate; 2, a device isolation oxide film formed on the semiconductor substrate 1; 3, source/drain regions formed in an active region surrounded by the device isolation oxide film 2 of the semiconductor substrate 1; 4, a gate oxide film formed on the semiconductor substrate 1; and 5, a gate electrode formed on the gate oxide film 4. The gate electrode 5 is made up of a polycrystalline silicon film 6 doped with a dopant, e.g., phosphorous, for determining its conductivity type, a titanium silicide film 7, and a tungsten silicide film which are stacked in the above order.
A method of manufacturing the NMOS transistor of the first prior art having the above-described construction will now be described in conjunction with FIGS. 18A and 18B. To begin with, the device isolation oxide film 2 is formed on the semiconductor substrate 1 by the LOCOS method. Next, the gate oxide film 4 having a thickness of 60 .ANG. is formed by oxidizing the top surface of the semiconductor substrate 1 by, for example, thermal oxidation. Then, a polycrystalline silicon film 6 that is doped with phosphorous at a dose of 5.times.10.sup.20 /cm.sup.2 as a dopant for determining its conductivity type is formed at a thickness of, for example, 800 .ANG. by CVD. A titanium silicide film 7 is then formed on the polycrystalline film 6 at a thickness of, for example, 150 .ANG. by sputtering. This is followed by formation of a tungsten silicide film 8 at a thickness of, for example, 800 .ANG. by sputtering (FIG. 18A).
Thereafter, the gate electrode 5 is formed by etching a desired area of the tungsten silicide film 8, the titanium silicide film 7, and the polycrystalline silicon film 6 by use of a photolithography technique (FIG. 18B). LDD layers are then formed by implanting, e.g., arsenic ions into the semiconductor substrate 1 being tilted at an angle of, e.g., about 40.degree. under the conditions of, e.g., 30 keV and 40.times.10.sup.13 /cm.sup.2. Side-wall oxide films 9 are formed by depositing a silicon oxide film at a thickness of 800 .ANG. by, e.g., CVD, and etching back the thus-formed silicon oxide film. The source/drain regions 3 are formed by implanting, e.g., arsenic ions, into the semiconductor substrate 1 under the conditions of 50 kev and 40.times.10.sup.15 /cm.sup.2. An NMOS transistor is completed by subjecting the substrate to a heat treatment of, e.g., 800.degree. C. and 60 minutes (FIG. 17).
FIG. 19 is a cross sectional view showing the construction of a second conventional semiconductor device, which is a DRAM cell. In the drawing, the same reference numerals are given to the corresponding elements of the first conventional semiconductor device, and the explanation thereof will be omitted here for brevity. Reference numeral 10 denotes diffusion layers formed in an active region surrounded by a device isolation oxide film 2 of a semiconductor substrate 1; 11, word lines formed on the semiconductor substrate 1; 12, a first interlayer insulation film so formed as to cover the word line 11; 13, a first contact hole formed through the first interlayer insulation film 12 to the top surface of the diffusion layer 10; and 14, a bit line so formed as to fill the first contact hole 13. The bit line 14 is made up of a polycrystalline silicon film 15 doped with a dopant, e.g., phosphorous, for determining its conductivity type, a titanium silicide film 16, and a tungsten silicide film 17 which are stacked in the above order.
Numeral 18 denotes a second interlayer insulation film so formed as to cover the bit line 14; 19, second contact holes formed through the first and second interlayer insulation films 12 and 18 to the top surface of the diffusion layer 10; and 20, capacitors so formed as to fill the respective second contact holes 19. Each capacitor 20 is made up of a storage node 21, a capacitor insulation film 22, and a cell plate 23 which are stacked in this order.
A method of manufacturing the DRAM cell of the second prior art having the above-mentioned construction will now be described in conjunction with FIGS. 20A-20C. First, the device isolation oxide film 2 is formed on the semiconductor substrate 1 by the LOCOS method. Then, the word lines 11 is formed with, e.g., a polycrystalline silicon film. The diffusion layers 10 are then formed on the semiconductor substrate 1 by implanting, e.g., arsenic ions into the semiconductor substrate 1. A first interlayer insulation film 12 is deposited at a thickness of 600 .ANG. by, e.g., CVD. The first contact hole 13 is formed by etching a desired portion of the first interlayer insulation film 12 to the top surface of the diffusion layer 10 by photolithography (FIG. 20A).
A polycrystalline silicon film 15 that is doped with a dopant, e.g., phosphorous, for determining its conductivity type at a dose of 5.times.10.sup.20 /cm.sup.2 is deposited at a thickness of 800 .ANG. by CVD. A titanium silicide film 16 is deposited at a thickness of, e.g., 150 .ANG. by sputtering, and a tungsten silicide film 17 is deposited at a thickness of, e.g., 800 .ANG. by sputtering (FIG. 20B). Subsequently, the bit line 14 is formed by etching prescribed portions of the polycrystalline silicon film 15, the titanium silicide film 16, and the tungsten silicide film 17 by photolithography (FIG. 20C).
A second interlayer insulation film 18 is deposited at a thickness of 5,000 .ANG. by, e.g., CVD, and the second contact hole 19 is formed by etching a desired portion of the first and second interlayer insulation films 12 and 18 to the top surface of the diffusion layer 10 by photolithography. The storage node 21 is then formed by depositing polycrystalline silicon that is doped with, e.g., phosphorous and has a thickness of 5,000 .ANG., and patterning the polycrystalline silicon film. The capacitor insulation film 22 is formed on the storage node 21 at a thickness of, e.g., 100 .ANG., and the cell plate 23 comprised of, e.g., a polycrystalline silicon film is formed at a thickness of 1,000 .ANG., thereby constituting the capacitor 20. As a result, a DRAM cell is completed (FIG. 19).
FIG. 21 is a cross sectional view showing the construction of a dual gate CMOS semiconductor of a third prior art. In this drawing, the same reference numerals are given to the corresponding elements of the conventional semiconductor devices set forth above, and the explanation thereof will be omitted here for brevity. Reference numeral 24 denotes a P well formed in an NMOS formation region I of a semiconductor substrate 1; 25, an N well formed in a PMOS formation region II of the semiconductor substrate 1; 26, N-type source/drain regions formed on the semiconductor substrate 1 in the NMOS formation region I; and 27, P-type source/drain regions formed on the semiconductor substrate 1 in the PMOS formation region II.
Reference numeral 28 denotes an NMOS gate electrode formed in the NMOS formation region I. The NMOS gate electrode 28 comprises an N-type polycrystalline silicon film 29 doped with a dopant, e.g., phosphorous, for determining a first conductivity type, a titanium silicide film 7, and a tungsten silicide film 8 which are stacked in the above order. Reference numeral 30 denotes a PMOS gate electrode formed in the PMOS formation region II. This PMOS gate electrode comprises a P-type polycrystalline silicon film 31 doped with a dopant, e.g., boron, for determining a second conductivity type, a titanium silicide film 7, and a tungsten silicide film 8 which are stacked in the above order.
A method of manufacturing the dual gate CMOS of the third prior art having the above construction will now be described in conjunction with FIGS. 22A-22C. The device isolation oxide film 2 is formed on the semiconductor substrate 1 by the LOCOS method. The P well 24 is formed by forming an opening in a resist film only in the NMOS formation region I using photolithography, and implanting, e.g., boron ions, through the opening while changing the implantation energy. The N well 25 is formed by forming an opening in a resist film only in the PMOS formation region I using photolithography, and implanting, e.g., phosphorous ions, through the opening while changing the implantation energy. Subsequently, the gate oxide film 4 is formed at a thickness of 60 .ANG. by oxidizing the top surface of the semiconductor substrate 1 by, e.g., thermal oxidation. A polycrystalline silicon film having a thickness of 800 .ANG. is then formed on the gate oxide film 4 by using, e.g., CVD. The N-type polycrystalline silicon film 29 is formed by forming an opening in a resist film only above the P well 24 using photolithography, and implanting, e.g., arsenic ions into the polycrystalline silicon film under the conditions of 50 keV and 4.times.10.sup.15 /cm.sup.2. The P-type polycrystalline silicon film 31 is formed by forming an opening in a resist film only above the N well 25 using photolithography, and implanting, e.g., boron ions into the polycrystalline silicon film under the conditions of 10 keV and 4.times.10.sup.15 /cm.sup.2 (FIG. 22A).
A titanium silicide film 7 having a thickness of, e.g., 150 .ANG. is formed by sputtering. A tungsten silicide film 8 having a thickness of, for example, 800 .ANG. is also formed by sputtering (FIG. 22B). The NMOS and PMOS gate electrodes 28 and 30 are formed by respectively etching prescribed portions of the N-type and P-type polycrystalline silicon films 29 and 31, the titanium silicide film 7, and the tungsten silicide film 8 by photolithography (FIG. 22C).
LDD layers are then formed by implanting, e.g., arsenic ions into the P well 24 in the NMOS formation region I under the conditions of 30 keV and 4.times.10.sup.13 /cm.sup.2 while tilting the semiconductor substrate 1 at 40.degree.. The side-wall oxide films 9 are formed by depositing a silicon oxide film at a thickness of 800 .ANG., by, e.g., CVD, and etching back the silicon oxide film. The N-type source/drain regions 26 are then formed by forming an opening in a resist film only in the NMOS formation region I using photolithography, and implanting, e.g., arsenic ions through the opening under the conditions of 50 keV and 4.times.10.sup.15 /cm.sup.2. The P-type source/drain regions 27 are formed by forming an opening in a resist film only in the PMOS formation region II using photolithography, and implanting, e.g., boron ions into through opening under the conditions of 10 keV and 4 .times.10.sup.15 /cm.sup.2. A dual gate CMOS is completed by subjecting the substrate to a heat treatment of, e.g., 800.degree. C. and 60 minutes (FIG. 21).
Because the semiconductor devices of the prior art have the above described constructions, they have various problems described below. To begin with, the dopants for determining the conductivity type contained in the polycrystalline silicon films 6, 15, 29 and 31 are diffused into the titanium silicide films 7 and 16 and the tungsten silicide films 8 and 17 which are formed on the polycrystalline silicon films as a result of a variety of heating processes carried out after the titanium silicide films 7 and 16 and the tungsten silicide films 8 and 17 have been formed. Eventually, the concentrations of the dopants in the polycrystalline silicon films 6, 15, 29 and 31 become low. As a result of this phenomenon, a depletion layer is formed across each of the interfaces between the respective gate electrodes 5, 28 and 30 and the gate oxide film 4, whereby the gate capacitance is increased, which in turn results in decreased current drive capability of the device and an increased threshold voltage. Further, the previously mentioned phenomenon results in an increased resistance of the bit line 14 and prolonged read time.
In the case of the dual gate CMOS, because the NMOS formation region I and the PMOS formation region II are formed as shown in FIG. 23, the previously mentioned phenomenon causes the N-type and P-type dopants, which have entered the titanium silicide film 7 and the tungsten silicide film 8 as a result of heat treatments carried out after the formation of these films, to mix with each other by diffusing. As a result, if a distance "d" between the NMOS formation region I and the PMOS formation region II is smaller than a desired value, the work functions of the gate electrodes 28 and 30 are changed to vary the PMOS and NMOS characteristics. To prevent such variations in the characteristics, the distance "d" should be made large. Further, it is necessary to prevent the NMOS and PMOS characteristics from varying even if the mutual diffusion of the dopants arise. However, a large distance between the two formation regions obstructs miniaturization of the device.
A native oxide film (not shown) of a few angstrom exists on the top surface of each of the polycrystalline silicon films 6, 15, 29 and 31. For this reason, the contact resistances between the titanium silicide films 7 and 16 and tungsten silicide films 8 and 17 and the polycrystalline silicon films 6, 15, 2 and 31 are increased. The increased contact resistance brings about an increase in the resistance value of each of the gate electrodes 5, 28 and 30, which in turn results in a drop of an applied voltage. The drop of the applied voltage leads to a decrease in current drive capability of the transistor. As for the bit line 14, an increased resistance prolongs the read time.